1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a technology effective when applied to a semiconductor memory device that uses vertical MIS (Metal Insulator Semiconductor) transistors.
2. Description of Related Art
The miniaturization of memory cell transistors is the most effective means for realizing higher integration of dynamic random access memory (hereinbelow abbreviated as “DRAM”). Miniaturizing the feature size (F) enables the reduction of the size of memory cell transistors and improves integration. In addition, compressing cell size by altering cell mode as in 6F2 and 4F2 cells is also important. In a 4F2 cell, vertical MOS (metal oxide semiconductor) transistors must be used as access transistors. In cells of the related art, storage nodes are present between word lines and provide a shielding effect, but when vertical MOS transistors are used, word lines are directly adjacent to each other. As a result, the capacitance between word-lines occupies a greater proportion of the total capacitance of word lines.
Problems that arise as a result will be explained using an example of the configuration of a memory array. The memory array of FIG. 1 is composed of a plurality of memory cells MC, memory cell MC being made up from one MOS transistor and one capacitor Cs. One of the source or drain of a MOS transistor is connected to bit line BL0, BL1, . . . BLn, the other of the source or drain is connected to storage node SN, and the gate is connected to word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. Adjacent parasitic capacitances C01, C12, C23, C34, C45, C56, and C67 of length L of the word line are present between each of the word lines.
In addition, sub-word drivers SWD for driving word lines are arranged alternately to the right and left at one end of each word line. In this case, when WL2 is selected as a word line selection operation, the level of this word line becomes high level, and the other non-selected word lines are maintained at low level. However, the levels of adjacent non-selected word lines WL1 and WL3 are raised due to the coupling noise generated through the parasitic capacitance C12 between word line WL2 and word line WL1 and the parasitic capacitance C23 between word line WL2 and word line WL3. The levels of non-selected word lines WL1 and WL3 that are adjacent to word line WL2 therefore increase and the data of memory cells that are connected to word lines WL1 and WL3 leak to bit lines, thereby raising the problem of the likelihood of data destruction.
In relation to this problem, twist connector WCA2 is provided in Japanese Patent Laid-open Publication No. 167572/2001 (hereinbelow referred to as Patent Document 1) for switching the order of arrangement of word lines among the word lines as shown in FIG. 2, whereby adjacent word lines are altered. For example, focusing on word line WL1, although the number of adjacent word lines increases to the four word lines of WL0, WL2, WL3, and WL6, the length of the portion that is adjacent to each word line is reduced by one-half and the parasitic capacitance is also reduced by one-half, whereby the coupling noise received by adjacent word lines can be reduced.
In addition, Japanese Patent Laid-open Publication No. 268173/94 (hereinbelow referred to as Patent Document 2) discloses that coupling noise received by adjacent word lines can be reduced by arranging a level-stabilizing circuit made up from a plurality of SGT (Surrounding Gate Transistors) for each word line to maintain adjacent word lines unchanged at a low level.
However, the advance in the miniaturization in DRAM and the employment of vertical MOS transistors in memory cells has led to an increase in the parasitic capacitance between adjacent word lines. In order to stabilize the operation of DRAM, a method such as described in Patent Document 1 must be employed to reduce the parasitic capacitance by repeatedly providing twist connectors for switching the order of arrangement of word lines. However, because memory cells MC cannot be arranged in the region below twist connectors, the repeated provision of twist connectors results in the drawback of increased chip size.
On the other hand, in Patent Document 2, although increasing the channel width of a level-stabilizing circuit or the arrangement of a plurality of level-stabilizing circuits can reduce coupling noise, both approaches entail the problem of increased chip size.